TWL4030 power scripts

Recommended sleep settings for OMAP3 boards
This provides the recommended sleep and active sequences for TWL5030 when connected to OMAP3430 or OMAP3630.

Also the setup time values that are recommended for OMAP in this configuration.

TWL5030 (PMIC) interface with OMAP3


The following block diagram shows the handshake signals used for controlling resources when going in and out of idle between the OMAP3430 and OMAP3630 (OMAP), TWL5030 (PMIC) and oscillator.

PMIC Device Group Assignment
TWL5030 has 3 device groups (P1, P2 and P3):

The following table shows the recommended change from the default device group assignments (highlighted in red):

PMIC Type Change
The following table shows the recommended TYPE2 changes from default (highlighted in red). It is not recommended to use TYPE because TYPE is used during the power up sequence of TWL5030. In all cases in TWL5030 when going from the wait-on state to the power-up state the TYPE registers are reset to default except when the wait-on state is entered using the devoff feature. Therefore if the devoff feature of TWL5030 is used then you must not modify the TYPE settings from default.

PMIC REMAP Change
The following table shows the recommended changes from default for remapping (highlighted in red). VDD1, VDD2 and VPLL1 are remapped to turn off.

Recommended Values on OMAP
The following values are the recommended OMAP settings with 26MHz SYS_CLK.

Workaround for TWL5030 Errata 27
The recommended sleep settings for OMAP3430 and TWL5030 on the OMAP3 platforms to avoid the glitch that may be seen when voltage scaling is performed.

TWL5030 Sleep Sequence (A2S)


When SYS_CLKREQ goes low during retention no resources will be affected since no resources are assigned to P3 only. Also ensure the HFCLKOUT resource goes to the sleep state before the CLKEN resource goes to the sleep state. This is to make sure that the switch from HFCLKIN to the internal oscillator is done while HFCLKIN is stable.

TWL5030 Active Sequence (S2A)


The same sequence is used for P12 and for P3 because they execute in parallel and we save time and have better control by allowing all resources to ramp up on the same event.

The oscillator specification on Zoom platforms has a 10ms ramp time. There is a measured delay of ~10 usec from SYS_CLKREQ going high to CLKEN going high from the singular message. We will round this up to one 32.768 kHz clock cycle (30.52 usec). Four broadcast messages are sent for CLKEN to allow us to get a total of 10.04ms for the delay where we need at least 10.03052 ms. TWL5030 supports a maximum delay of 3.418 ms. TYPE is not used to differentiate resources so it is set to 0x0.

TWL5030 Device Group Changes


Voltages VDD1, VDD2 and VPLL1 are assigned to P1 and P3 because P3 (SYS_CLKREQ) ramps up before P1 (SYS_OFFMODE). This allows us to control these resources better than if they were assigned to P1 only because it is essential that VDD1 and VDD2 do not ramp up until after HFCLKIN is stable and after HFCLKOUT is enabled. Note the HFCLKOUT will only turn off in OFF mode by assigning it to P1 and P3.

OMAP3430 Setup Times
When going into OFF mode the following settings should be used.

PRM_CLKSETUP must always equal PRM_VOLTOFFSET + PRM_VOLTSETUP2.

PRM_VOLTOFFSET is arbitrarily set to 488.32 usec. But the measured value was 516 usec so we will use the lower of the two in the formula below to be conservative. This value can be changed but will result in changing the PRM_CLKSETUP based on the previous formula. PRM_VOLTSETUP2 is calculated as follows:

PRM_VOLTSETUP2 was rounded up to 11.079 ms to allow some tolerance.

Settings to Change for Different Oscillator
The following changes will be needed if an oscillator is used that has a different ramp time.

1. TWL5030 S2A sequence – need to change the delays for the four broadcast messages to match the oscillator datasheet ramp time + 30.52 usec. Round up if needed. For the Zoom platforms the datasheet shows 10 msec. TWL5030 only supports up to 3.418 ms delays. So in this case we have 4 broadcast messages, first two with 3.418 ms delay and the third with 3.174 ms delay and a fourth with 30.52 usec to get a total of 10.04 ms delay.

2. PRM_VOLTSETUP2 should be adjusted. This value can be adjusted up or down based on the values in this white paper using an oscillator with a 10 ms ramp time but it may be best to measure on your platform the time from SYS_OFFMODE going high to when the voltages VDD1 and VDD2 are stable. On the Zoom we measured ~10.5 msec. Therefore a value of 11.079 ms is safe.

3. PRM_CLKSETUP – this value must always equal PRM_VOLTOFFSETUP + PRM_VOLTSETUP2.

4. The circuit that is used to gate the oscillator using CLKEN needs to be analyzed. In some instances CLKEN may be used to enable/disable a power supply regulator that will power the oscillator. If this is the case then the regulator turn on time needs to be added to the oscillator data specification ramp time.

Testing TRITON script changes
Since the voltage layer is evolving to a new design, the voltage dependant changes required for the TRITON script are not incorporated in this patch series. So we can test this TRITON script patch with a separate patch for voltage layer changes.