J6 Resource Allocation

=J6 Resource Allocation for 6AJ 1.x release=

Interrupt Mapping
The interrupt mapping for MPU, IPU1 and IPU2 can be found here [[Media:Irq_mappings.pdf]].

The content of this file was obtained from omapconf (omapconf dump crossbar all)

SDMA Mapping
The SDMA mapping can be found here [[Media:Sdma_mapping.pdf]].

The data for this file was obtained from u-boot sources (board/ti/dra7xx/evm.c)

EDMA
EDMA is not used by TI software and is free to use.

IP used by Android
All the information below has been gathered from the device tree (arch/arm/boot/dts/dra7.dtsi and dra7-evm.dts)

Timers
There are 16 GP Timers in the device: Timer1 through Timer 16. Timers used in Android:
 * Timer1, Timer 10, Timer 12 by kernel.
 * The following timers are used by RemoteProc:

6AL.1.x

 * The following timers are used by RemoteProc in 6AL.1.x:

McASP
There are 8 McASP modules (McASP1- McASP8) Use McASP 4-8 for more tolerance to interconnect latency (Using AFIFO through DAT port).

McASP modules used in Android:
 * McASP2, McASP3 - Radio
 * McASP6 for Audio.
 * McASP7 for Bluetooth.

I2C
There are 5 I2C controllers in the device. I2C controllers used by Android:
 * I2C1 - PCF8575 I/O Expander(LCD), TLC59108.
 * I2C2 - PCF8575 I/O Expander (HDMI), TLV320, Omnivision OV10633, FPD, TVP5158 encoder (JAMR3 only), OV10635 (VisionB only), LVDS OV10635 CAM1,2,3,4,5,6 (VisionB only), CAM FPD Deserializers 1,2,3,4,5,6 (VisionB only)
 * I2C4 - Radio Tuner

USB
There are 4 instances of USB in the system PHY and HS/FS (USB2.0) PHY PHYs PHYs.
 * USB1: SuperSpeed (SS) USB 3.0 Dual-Role-Device (DRD) subsystem with integrated SS (USB3.0)
 * USB2: High-Speed (HS) USB 2.0 Dual-Role-Device (DRD) subsystem with integrated HS/FS PHY
 * USB3: HS USB 2.0 Dual-Role-Device (DRD) subsystem with ULPI (SDR) interface to external HS/FS
 * USB4: HS USB 2.0 Dual-Role-Device (DRD) subsystem with ULPI (SDR) interface to external HS/FS

Default Android configuration: Note: USB1 can be changed from Device to Host mode by applying the patch http://review.omapzoom.org/#/c/34142/ Note: The signals representing USB3 and USB4 are not brought out to connectors on J6EVM.
 * USB1 is configured in Device mode.
 * USB2 is configured in Host mode.

UART
There are 10 UART modules in the device UART1- UART10. Modules used in Android: Note:: The first 6 UART device nodes are enabled in the dts file even though only 3 and 1 are used. This exhausts the maximum number of UARTS that can be enabled at a time from the kernel. This is currently a driver limitation. In order to enable more UARTs, one of the unused (2,4,5, or 6) could be safely removed from the dts file and the desired UART can be enabled.
 * UART3 for Bluetooth/GNSS
 * UART1 for serial console output

GPIO
The general-purpose interface provides 8 GPIO banks. Each GPIO module provides 32 dedicated general-purpose pins with input and output capabilities. GPIO usage in Android

I/O Expanders

P0 - P3 Touch Screen LCD, P0 – Early Camera Reverse Gear GPIO P4 - P14 Unused P15 LCD Power Down P16 to P17 Unused
 * PCF1 on I2C1

P0 FPDLink P1 to P15 Unused P16 kim P17 Unused
 * PCF2 on I2C1

P1 Unused P2 - P3 by Omnivision P4 - P5 by HDMI P6 - P17 Unused
 * PCF on I2C2

Note: In case of using the 10" display (for J6Eco), the gpio bank 1 pin 15 is used.

Mailboxes
DRA7xx has 13 system mailboxes, of which 1, 5, 6 are used.

OCMC_RAM
OCMC_RAM Address Range : 0x40300000 – 0x4037FFFF is not used by TI software.

Pad conf settings
Pad conf settings can be found here [[Media:Pad_config.pdf]]. The data for this file was obtained from u-boot sources (board/ti/dra7xx/mux_data.h) and device tree.

IPU Memory Mapping for Bit-banding Region
The ARM Cortex-M4 memory map includes a bit-banding region of memory from 0x4000:0000 to 0x400F:FFFF and 0x4200:0000 to 0x43FF:FFFF. Here is a Cortex-M4 memory map picture from ARM: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0553a/CHDBIJJE.html Many Vayu components running on the IPUs, including IPC, must access peripherals physically located in this bit-banding region. As a result, these accesses must be performed indirectly using a virtual memory address, mapped using the IPU's AMMU. Many of the components aligned on mapping this memory using one Large AMMU page that maps 512M of physical memory beginning at 0x4000:0000 to virtual memory beginning at 0x6000:0000. Then the components (by default) access the peripherals using the 0x6XXX:XXXX address space.

IPC specifics
IPC follows the convention of, by default, accessing memory physically located at 0x4XXX:XXXX using virtual memory at 0x6XXX:XXXX. You can see an example of this here - note the mailbox addresses configured here are in the 06XXX:XXXX range: http://git.ti.com/cgit/cgit.cgi/ipc/ipcdev.git/tree/packages/ti/sdo/ipc/family/vayu/InterruptIpu.xs In that same file, you can see that these addresses are configurable, and the default 0x6XXX:XXXX addresses are only used if other addresses haven't already been configured by the system integrator (e.g. in a .cfg script). Users can override these default mailbox addresses using the ti.sdo.ipc.family.vayu.InterruptIpu module's mailboxBaseAddr[] array, documented here: http://software-dl.ti.com/dsps/dsps_public_sw/sdo_sb/targetcontent/ipc/latest/docs/cdoc/ti/sdo/ipc/family/vayu/InterruptIpu.html#metamailbox.Base.Addr